1. Field of the Invention
The present invention relates generally to a data transfer device and, more particularly, to a peripheral component interconnect (PCI) host bridge device.
2. Description of the Related Art
In 1995, version 2.0 of the peripheral component interconnect (PCI) bus specification was replaced by version 2.1. This new version introduced new requirements intended to better control bus latency and performance. For example, the new version only allows a certain amount of cycles during which a PCI target device has to transfer data in response to a request from a master device. If the target device cannot respond within the allowable time (e.g., 16 cycles), then the target device must instruct the master device to resend the request at a later time. This 16-cycle constraint is intended to free the PCI bus for other transactions instead of holding the bus in a wait state until the data is fetched. These new requirements, however, engender new technical problems that are yet to be solved.
One solution to these technical problems is to re-design the PCI host bridge (PHB) to accommodate the new requirements. A PHB is a hardware that interconnects a system bus to a PCI bus to receive/transmit input/output (I/O) data. The PHB accepts I/O commands from the system bus and controls the execution of these commands on the PCI bus. Conversely, the PHB accepts direct memory access (DMA) commands from the PCI bus and controls the execution of the DMA commands on the system bus. The PHB has an internal arbiter for controlling the PCI bus along interrupt support logic. The PHB contains data buffering for processor to I/O commands (i.e., loads, stores) along with data buffering and an internal data cache for DMA accesses to system memory.